The description relates to signal compensation for flat panel displays.
Referring to FIG. 1, an example of a liquid crystal display 100 includes an array of rows and columns of pixel circuits 13, each pixel circuit 13 corresponding to a scan line (e.g., 20a, 20b, 20c, or 20m) and a data line (e.g., 16a, 16b, or 16n). The scan lines (collectively referenced as 20) are driven by a scan driver 22, and the data lines (collectively referenced as 16) are driven by a data driver 10. Each pixel circuit 13 includes a transistor (e.g., 12ba, 12bn, or 12ca) and a storage capacitor (e.g., 14ba, 14bn, or 14ca). A timing controller 24 controls the scan driver 22 to send scan signals on the scan lines 20 to successively turn on the transistors 12 of each row, allowing the data driver 10 to send pixel data through the data lines 16 to corresponding storage capacitors 14. For example, the gate electrode of the transistor 12ba is connected to the scan line 20b. The transistor 12ba functions as a switch positioned between the storage capacitor 14ba and the data line 16a. When the transistor 12ba is turned on (e.g., by sending a logic high scan signal on the scan line 20b), the storage capacitor 14ba is connected to the data line 16a and is charged to the voltage level on the data line 16a. The pixel data stored in the storage capacitors 14 correspond to gray levels of pixels of an image shown on the display 100.